This invention relates generally to applying gas cluster ion beams (GCIB) to improve the quality of electrical interconnections in integrated circuitry, and, more particularly to improving electrical interconnections by etching and/or cleaning the bottoms of interconnect vias between integrated circuit interconnect layers in circuits employing the dual damascene process, or the like, prior to forming the interconnecting via plug.
The use of a gas cluster ion beam for etching or cleaning planar material surfaces is known (see for example, U.S. Pat. No. 5,814,194, Deguchi et al.) in the art. For purposes of this discussion, gas clusters are nano-sized aggregates of materials that are gaseous under conditions of standard temperature and pressure. Such clusters typically consist of aggregates of from a few to several thousand molecules loosely bound to form the cluster. The clusters can be ionized by electron bombardment or other means, permitting them to be formed into directed beams of known and controllable energy. The larger sized clusters are often the most useful because of their ability to carry substantial energy per cluster ion, while yet having only modest energy per molecule. The clusters disintegrate on impact, with each individual molecule carrying only a small fraction of the total cluster energy. Consequently the impact effects of large clusters are substantial, but are limited to a very shallow surface region. This makes ion clusters effective for a variety of surface modification processes, without the tendency to produce deeper subsurface damage characteristic of monomer ion beam processing.
Means for creation of and acceleration of such GCIBs are described in the reference (U.S. Pat. No. 5,814,194) previously cited. Presently available ion cluster sources produce clusters ions having a wide distribution of sizes, n (where n=the number of molecules in each clusterxe2x80x94in the case of monatomic gases like argon, an atom of the monatomic gas will be referred to as a molecule and an ionized atom of such a monatomic gas will be referred to as a molecular ionxe2x80x94or simply a monomer ionxe2x80x94throughout this discussion).
In the semiconductor industry, increasing circuit density drives progress toward smaller and smaller dimensions and larger numbers of transistors placed in an individual device. The challenges to interconnect these transistors becomes increasingly difficult. Some of the problems faced with denser interconnections are increased heat dissipation, greater power consumption, and longer signal delays resulting from higher resistance in the interconnects. Moving to the use of lower resistivity metals for the interconnections helps to alleviate these problems, and the dual damascene Cu interconnect scheme is becoming favored. However, in common modern interconnect structures a diffusion barrier material must be employed to encapsulate the metal conductor to prevent diffusion of the conductor metal atoms so as to avoid undesired contamination of the semiconductor materials. Typical barrier materials used are thin films of materials such as Ta, TiN, TaN, etc., which have significantly higher electrical resistivities than the Al or Cu used as the interconnect metal. Dielectric materials like SiC and SiN also make effective diffusion barriers and have advantages but have not so far found wide acceptance because they have much higher electrical resistance and do not provide low resistance electrical continuity at the bottoms of electrical interconnect vias. Usually, cylindrical vias form the connections between interconnect metal layers, and barrier material films are used inside the vias. The barrier materials must first be deposited in such a way as to form a continuous layer on the sidewalls of the via. Typically this results in an additional amount also deposited at the bottom of the contact (bottom or base of the via). This film at the bottom of the contact is unnecessary as a diffusion barrier since the adjacent material is the interconnect metal, and unfortunately contributes an increased resistivity obstruction in the electrical current path. The interface resistance between the interconnect metal and the barrier material also exacerbates this problem. The Semiconductor Industry Association""s International Technology Roadmap for Semiconductors (ITRS 2000) projects that barrier/cladding thickness must be decreased to from 13 nm to 10 nm by 2005 and to 0 nm by 2008 in order to meet industry goals.
Another significant source of high contact resistance is residue of materials from previous process steps in the manufacturing of the interconnect structures that tend to be trapped or otherwise remain in the bottom of the contact via structures. These residues generally consist of high resistivity materials such as organic compounds from photo-resists, and by-products of etching of other layers in the film stack. The removal of this contamination layer at the bottom of a contact structure is another significant means for improvement in IC performance.
In modern interconnect technology, via holes are etched through the inter-metal dielectric layer between interconnect layers, using a mask. After etching, the bottom of the vias have residual byproducts (such as for example, SiN and CuO in a dual damascene process) that can adversely affect via interconnect resistance. It is problematic to effectively get etchants to the bottoms of the interconnect vias. Plasma etching or cleaning technologies operate in the range of pressures greater than 10xe2x88x923 Torr. At such pressures the mean free path of the ion is short (less than about 5 cm for Ar at 10xe2x88x923 Torr) and make many collisions that result in poor etching directionality. Thus the reactive ions tend to attack the interconnect via sidewalls and can undesirably reduce the sidewall barrier material thickness. This increases the risk of a breach in the barrier. It is also very difficult to get reacted material evacuated from the bottom of the contact. After the cleaning step, a barrier material is deposited and then the via is filled with the plug material (for Al interconnects) or, for Cu interconnects, a seed Cu layer is deposited and then the via is then filled with a Cu plug. Any residues can dramatically degrade the interconnect via characteristics.
GCIBs having sufficient flux density to clean or etch planar surfaces or surfaces having modest deviations from planarity are readily generated with existing technology. Similarly, more conventional monomer ion beams capable of etching or milling or cleaning planar or near-planar surfaces are also readily generated. When such beams are used to clean or etch surfaces, the cleaning or etching generally results from a sputtering process or in the case where a reactive ion species is employed, reactions of the ions with the surface can work in combination with a sputtering process. Because of the large aspect ratios of interconnect vias it has not been practical to clean or etch the bottoms of interconnect vias without undesirable effects on the sidewalls of the vias. Directed beams of conventional monomer ions are not readily produced with high flux densities necessary for practical cleaning or etching rates while simultaneously having a high degree of directionality (low beam emittance and low beam divergence). Energetic monomer ions striking a surface at a grazing angle tend to have a higher sputtering rate much higher than they do when they strike a surface at normal or near-normal incidence. Accordingly, when such ions are directed down an interconnect via hole, sputtering of the sidewalls tends to proceed at a higher rate than sputtering of the bottom.
It is therefore an object of this invention to provide a method to effectively and efficiently clean the bottoms of interconnect vias without significantly degrading the integrity of the barrier material film on the interconnect via sidewalls.
It is also an object of this invention to provide a method to effectively and efficiently clean or etch the bottoms of interconnect vias without significantly etching the sidewalls of the interconnect vias.
It is a further object of this invention to provide a method to etch away the barrier material film and any contaminants at the bottoms of interconnect vias without significantly degrading the integrity of the barrier material film on the interconnect via sidewalls in order to make lower resistance contacts between interconnect layers.
It is a still further object of this invention to provide an electrical interconnect via for integrated circuits that uses dielectric or high resistivity diffusion barrier materials.
The objects set forth above as well as further and other objects and advantages of the present invention are achieved by the embodiments of the invention described hereinbelow.
One embodiment of the present invention provides a method for processing a recess, such as a trench or via, which extends into a substrate to a base or bottom, comprising the step of directing a gas cluster ion beam through the recess on to the base or bottom. In one refinement, the recess is coated with a barrier material on a sidewall and the base or bottom of the recess, and further wherein the step of directing is used for etching the barrier material from the base or bottom of the recess without substantially etching the barrier material from the sidewall of the recess. Further, the recess may be an opening in an inter-metal dielectric material, and further wherein the barrier material is a highly resistive, diffusion barrier layer.
In another refinement, the step of directing includes moving the gas cluster ion beam with respect to the substrate while maintaining the substrate substantially normal to the gas cluster ion beam.
In yet another refinement, the step of directing is used for removing residue material from the base or bottom of the recess after formation of the recess in the substrate.
In still another refinement, the recess extends into the substrate in one or more directions to the base or bottom, wherein the step of directing is performed approximately parallel to said one or more directions.
In still another refinement, the step of directing is performed in an atmospheric pressure of less than 10xe2x88x924 Torr.
In still another refinement, the gas cluster ion beam clusters may include an inert gas and a reactive gas. The reactive gas may include or a halogen or halogen-bearing gas, and the mixture may include at least one of hydrogen or oxygen.
In another embodiment, the present invention provides a substrate having a recess such as a trench or via, extending into the substrate, and includes the recess having a base or bottom processed by a step of directing a gas cluster ion beam through the recess on to the base or bottom. In a refinement, the recess has at least one sidewall and is first coated with a barrier material on the sidewall and the base or bottom, wherein the step of directing is used for etching the barrier material from the base or bottom of the recess without substantially etching barrier material from the sidewall of the recess. In yet a further refinement, the recess is an opening in an inter-metal dielectric material, wherein the barrier material is a highly resistive, diffusion barrier layer. In still a further refinement, the substrate further includes a conductive interconnect located within the recess and surrounded along at least one sidewall by the highly resistive, diffusion barrier layer, wherein the conductive interconnect includes a relatively low resistance connection at the base or bottom of the recess
In another refinement, the substrate includes a surface proximal to the recess and on which the barrier material is also coated, wherein the step of directing is used for thinning of the barrier material on the proximal surface.
In yet another refinement, the step of directing includes forming the gas cluster ion beam from an inert gas and a reactive gas to reduce re-deposition of etched material.
In another embodiment, a method for removing diffusion barrier layer material from a bottom of a trench or via structure during fabrication of an integrated circuit, includes:
providing an integrated circuit substrate for forming an integrated circuit, the substrate containing at least one trench or via structure at a surface of the substrate, the at least one trench or via structure having a bottom comprising diffusion barrier layer material and at least one sidewall comprising a diffusion barrier layer material;
forming an accelerated and directed gas cluster ion beam in a reduced pressure chamber, the gas cluster ion beam having a beam path;
disposing the surface of the substrate in the reduced pressure chamber and in the gas cluster ion beam path; and
irradiating the bottom of the at least one trench or via structure with the gas cluster ion beam to remove diffusion barrier layer material from the bottom of the at least one trench or via structure.
In a refinement, the diffusion barrier layer material comprises at least one of the group (Ta, TaN, TiSiNx, SiC, and SiN).
In still another embodiment, an electrical interconnect via in an inter-metal dielectric substrate includes a sidewall surrounded by a highly resistive, diffusion barrier layer, and a base or bottom forming a relatively low resistance connection.
For a better understanding of the present invention, together with other and further objects thereof, reference is made to the accompanying drawings and detailed description and its scope will be pointed out in the appended claims.